The present invention is generally related to semiconductor device fabrication, and, more particularly, the present invention is related to method for removing crystal defects in a doped dielectric surface and improving surface planarity using plasma etching.
Throughout the evolution of integrated circuits, one aim of device scaling has been to increase circuit performance and to increase the functional complexity of the circuits. At the outset, scaling down of active device sizes was a very effective means of achieving these goals. Eventually, however, the scaling of active devices became less gainful, as the limitations of the circuit speed and maximum functional density depended more on the characteristics of the interconnects than on the characteristics of the scaled devices. In addition, various aspects, such as silicon utilization, chip cost, and ease and flexibility of integrated circuit design have also been adversely affected by limitations of interconnect technology.
It is believed that most approaches to lifting these limitations have predominantly involved the implementation of multilevel-interconnect schemes. In the course of integrated circuit evolution, the maximum number of devices per chip has steadily increased, mainly as a result of the increase in functional density. Typically, functional density is referred to as the number of interconnected devices per chip area, while the number of devices per chip area is referred to as the active device density. As the minimum feature size on integrated circuits has decreased, the active device density has also increased.
Eventually, a burdensome condition has been reached in which the minimum chip area has become interconnect-limited. That is, the area needed to route the interconnect lines between the active devices has exceeded the area occupied by the active devices. Thus, continued shrinking of active devices has produced less circuit performance benefits. To overcome that issue, multilevel-interconnection within the integrated circuits has been implemented, and as additional levels are added to multilevel-interconnection architectures and circuit features are scaled to submicron dimensions, the demands regarding the required degree of planarization for surfaces of semiconductor wafers continue to grow.
The term planarization is generally well known to those skilled in the art. Those skilled in the art are also familiar with the fact that there are varying degrees of planarization. A planarized surface, as used herein, shall mean a substantially planar surface rather than an absolutely planar surface. Thus, a surface with a higher degree of planarization would be closer to being absolutely planar than a surface with a lower degree of planarization. The surface planarization may be implemented in the conductor, the dielectric layers, or both. As the number of levels in an interconnect technology is increased, the stacking of additional layers on top of one another produces a topography more vulnerable to roughness and other surface defects. Without planarization, the irregularities that result on the wafer surface from the stacking of layers can lead to topography conditions that would eventually reduce the yield of circuits to unacceptably small values.
To overcome the foregoing issues, various planarization techniques are widely used to achieve a high degree of global planarization. One such technique is chemical mechanical polishing (CMP), which consists of a combination of applying chemicals to the dielectric layer and mechanically polishing the wafer. Although very effective for removing any selected portion of the overlying dielectric across the wafer and providing substantially global planarization, CMP is a relatively time consuming and expensive process. For example, the CMP process generally needs to be closely monitored throughout the production and customized each time a different device is produced. This results in high production costs and lost time as the fabrication equipment must be re-calibrated with each successive lot of wafers.
Another difficulty that integrated circuit manufacturers have encountered in the fabrication of the dielectric generally interposed between a substrate and metallized conductive layers is product yield loss due to the formation of crystallite irregularities at the surface of the topmost layer of the dialectric. For example, the dielectric may comprise a base layer of undoped glass followed by one or more layers of doped glass Previous attempts to remove such crystal defects have involved using wet etching techniques. Unfortunately, such wet etching techniques have at best only been partially effective due to the anisotropic etching around the defects that may result in leaving a substantial number of undesirable surface holes or may even create additional defects on the surface of the doped dielectric.
In view of the above-described issues, it would be desirable to provide a method that allows for substantially removing the crystallite irregularities that may appear on the surface of any doped dielectric layers. It would be further desirable if such technique, in addition to substantially removing any such crystals, would simultaneously allow for improving the planarity of the surface of the semiconductor wafer so as to either avoid altogether any costly and time consuming planarization technique or at least significantly reduce the level of planarization that may still be required using known techniques, such as CMP. In either case, this would result in substantially reducing wafer fabrication costs and time.
Generally speaking, the foregoing needs are fulfilled by providing in one exemplary embodiment of the invention, a method for making a semiconductor device that allows for depositing a first layer of a doped dielectric. The method further allows for executing plasma etching so that one or more etchant gases flow over the first layer of doped dielectric. A second depositing step allows for depositing a second layer of doped dielectric over the plasma etched layer.
The present invention further fulfills the foregoing needs by providing in another aspect thereof, a semiconductor device including a first layer of doped dielectric, wherein said first layer is processed using plasma etching to form a plasma-etched layer. The semiconductor device further includes a second layer of doped dielectric deposited over the plasma-etched layer, wherein an interface boundary between said first and second layers comprises a respective indentation.
In yet another aspect thereof, the present invention provides a semiconductor device including a first layer of doped dielectric, e.g., Boro Phospor Silicate Glass having an upper surface, and a second layer of doped dielectric, e.g., Boro Phosphor Silicate Glass, deposited directly on the first layer.